Generally, buck power converters or buck regulators are used to generate power outputs for microelectronic devices. Although other converter topologies such as boost, buck boost, and the like are available, buck converters are often used because the buck converter topology is relatively efficient and provides high current swing (di/dt) capability. When providing a microelectronic circuit such as a microprocessor, for example, with a regulated voltage, current swing di/dt and response time are very important considerations in selecting the power converter. The output inductor value of the regulator determines the di/dt capability of the regulator. This inductor value also determines the operation boundary between the continuous conduction mode (“CCM”) and the discontinuous conduction mode. In CCM, the current flowing through the inductor is continuous; the load is demanding current at some level that requires input current from the supply for each cycle of the switched converter. In DCM, the load is demanding no, or light, current output. In this mode, the inductor current is not continuous but drops to zero. This phenomenon indicates that the load demand is light enough that an entire cycle of the switching converter may pass without the need for any additional power input from the supply into the converter.
FIG. 1(a) depicts, for illustrative purposes, a buck converter topology known in the prior art and described as an asynchronous buck converter. In FIG. 1(a) the high side driver M1 receives a pulse width modulated (PWM), usually a constant frequency square wave gating signal at its gate. In response, transistor M1 provides current into inductor L. In a CCM mode operation where the load is taking current out at a regular rate, the output voltage is maintained by a controller IC (not shown) that compares the output voltage Vo to a reference voltage (also not shown here for simplicity). The controller IC then changes the pulse width of the PWM signal to the gate of transistor M1 to provide the needed current. In this manner, the circuit continuously provides current to the load. If the output voltage Vo drops, additional power into the load is provided by a wider pulse signal on the high side driver M1 to compensate. If the output voltage Vo rises beyond the reference voltage, the controller then modifies the PWM pulse signal. The gating signal to the high side driver is narrowed or shorter in time, providing less energy into the inductor and the output capacitor and thus, the output voltage will again fall to the reference value.
When the load demands no, or a low, current, the circuit operates in a low voltage output situation (since Vo=the load current times the load resistance, shown as RL). In this situation, the asynchronous topology of FIG. 1(a) exhibits some inefficiency because the diode has a 0.7V drop across it. These inefficiencies may be tolerable if the load typically does not operate in a light load condition. However, for situations where the load is often operated in a light load condition, for example for a microprocessor that has a “sleep” or standby mode, these inefficiencies are not acceptable.
In response to the inefficiencies in the asynchronous buck converter, the synchronous buck converter topology was developed. In this converter, the diode of the asynchronous buck converter is replaced with another device, typically a MOSFET. This device is usually referred to as a “synchronous rectifier” or “SR”; in some literature the term “low side driver” may be used. FIG. 1(b) illustrates this topology. In FIG. 1(b) M2 is the SR. This SR driver will have a low resistance (low RDSON) and by gating signals to both the high and the SR, the controller IC (not shown) may efficiently control the voltage Vout for a variety of conditions.
However, the light load condition still presents problems with the synchronous buck converter and efficiency. FIG. 2 depicts the current (inductor current IL) and voltage (taken at the middle node labeled “phase” in FIG. 1(b) in the light load current or DCM mode of operation in a synchronous buck converter.
In FIG. 2, it can be seen at the point labeled T1 that the current IL through the inductor L of FIG. 1(b) becomes negative during a portion of the cycle. Negative current IL means current is flowing from the output circuitry and into ground or in some circuit topologies, back to the positive supply voltage node. This essentially means the output capacitor Co, see FIG. 1(b), is being discharged into ground through the current conduction path of synchronous rectifier M2. This loss phenomenon did not occur in the asynchronous buck topology of FIG. 1(a) because the diode (rectifier) is unidirectional, that is, current is not allowed to flow in that direction. Ideally the SR in the synchronous buck converter of FIG. 1(b) would be operated to emulate the diode in the asynchronous buck converter of FIG. 1(a) and prevent the current loss phenomenon.
To improve the efficiency of the synchronous buck converter, attempts are made to shut off the gating signal to the SR (M2 in FIG. 1(b)), typically a MOSFET transistor, when the current polarity through the inductor changes (indicating the load is discharging to ground). In this manner, energy stored in the output capacitor is not lost, but maintained in the output circuit for later use.
Looking at FIG. 2, it can be seen that the point in time that current flow should stop is the “zero crossing” point of the IL trace, labeled T1. Conveniently, the voltage at the phase node also crosses zero at this point, so that voltage sensing approaches may be used to identify this point where the output capacitor is starting to discharge. Prior art circuits typically attempt to stop current flow at this point by sensing it. However, present approaches to controlling the turn off time of the SR are sensitive to delays in the logic or buffers, voltage and temperature variations, and device characteristics of the SR device. These characteristics deleteriously affect the circuit operation.
With reference now to FIG. 3, a prior art solution to improving the operation of a synchronous buck converter in light load or DCM condition is shown. In FIG. 3, a circuit 11 is provided coupled between the driver or driver/controller IC (not shown) that provides the PWM signal used to form gating signals to control the high side driver and the SR. Circuit 11 includes a logic driver 13 that outputs gating signals GSR and GHS. Buffers 21 and 19 coupled to provide gating signals labeled High Side and SR, and these are coupled to the drivers M1 and M2. Circuit 11 also provides a comparator 17 coupled to the “phase” node at the intersection between the high side driver and the SR and the output inductor L. This comparator circuitry 17 provides the zero crossing detection that is intended to improve the efficiency of the buck converter under lightly loaded or DCM conditions.
The comparator 17 has an optional enable input also tied to the logic driver 13, so that the comparator is only enabled when the logic driver is sending an active GSR signal SR to M2.
The approach taken in the circuit of FIG. 3 is to make the synchronous buck converter operate similarly to the asynchronous buck converter in DCM mode, used for lightly loaded conditions, where the load does not require the converter to provide energy every cycle. Essentially the control of the SR device M2 should be performed such that current will not flow out of the load into ground, that is, the SR M2 should emulate the diode of the asynchronous buck converter. This “diode emulation” is accomplished by attempting to turn off the SR transistor M2 to block current IL from flowing in a negative direction from the inductor L.
Comparator 17 compares the voltage on the “phase” node to a reference voltage. In a simple approach, the reference voltage would be set at 0 volts. However, to compensate for the circuitry which may include a voltage offset or a delay, the reference voltage −Vref may be modified to be less than or greater than zero. This is done to make the circuit operate in a more efficient manner in a practical system. This is a simple compensation, or manual trimming, approach.
When the comparator 17 detects the zero voltage condition on the phase node, the AND gate 15 will shut off the gating signal through the low side buffer 19 and thus shut off the SR M2. Although shown very simply here, additional enable logic may be used to indicate to the comparator that the circuit is in DCM mode so that the comparator does not interfere with the gating signal when the circuit is operating in CCM mode. In any event the EN signal to the comparator, in conjunction with the operation of AND gate 15, will turn off the gating signal to the SR device at time T1 in FIG. 2, thus using voltage sensing on the phase node to locate the zero crossing point in the current trace of FIG. 2.
The prior art circuit of FIG. 3 is dependent on a fixed reference voltage Vref. The circuit is known to be sensitive to delay, temperature, noise and process variations. Further, the voltage at the phase node is dependent on the current path or RDSON resistance of the SR transistor M2, which may vary with temperature as well. Although this prior art approach is somewhat better than the basic synchronous converter of FIG. 1(b), inefficiencies still remain
FIG. 4 is a timing diagram for a simulation of a buck converter as in FIG. 3 illustrating the phase node voltage sensing approach in operation. The top trace of FIG. 4, labeled “phase (V)”, illustrates a detailed view of the voltage at the phase node. The second trace from the top, labeled “phase, Vout”, illustrates the phase node voltage and the output voltage taken together.
The third trace from the top, labeled IL, illustrates a timing diagram of the load current (in amps). The bottom trace of FIG. 4, labeled “GHS, GSR” illustrates the voltages of the gating signals output by the control circuit 11 in FIG. 3 to the transistors M1 and SR.
In operation, the comparator 17 will detect the point when the phase node voltage and the output voltage are equal, while the SR gating signal GSR is high (EN into the comparator). At this point in time, the AND gate 15 will cause the SR device to turn off, thereby preventing current flow into the SR device. The load current IL then cannot go below zero. In FIG. 4, this occurs at time T1, where the operation of the zero crossing detection circuits is shown by the flat bottom in the load current IL at about 0 Amps.
The topology of the buck converter of FIG. 3 is used only as one illustrative example of the zero crossing detection principle used to cause the “diode emulation”. The same principle of determining the zero crossing detection for the output current using voltage sensing of the phase node, in relation to another voltage, may be applied to other common synchronous converter topologies.
FIG. 5 depicts a prior art boost topology switching converter circuit with phase node voltage sensing. Similar reference designators are used for like elements that are shown in FIGS. 1, and 3. In FIG. 5 positive supply voltage PVCC is coupled through an inductor L to the phase node. Synchronous rectifier SR couples the voltage at the phase node to an output terminal Vo, to supply current into the load RL, and output capacitor Co. A driver M1 will couple the phase node to ground in response to a gating signal GLS from Driver Logic 13. (Note that buffers 19, 21 of FIG. 3 will typically be present at the outputs of the Driver Logic 13 to drive the power devices M1, M2 but are omitted here for clarity). Comparator 17 compares the output voltage Vo to the voltage at the phase node, and when enabled by the gating signal GSR provided by the Driver Logic 13, 17 will output a compare signal. AND gate 15 will turn OFF the SR device when the comparator is enabled and a match between the voltages at “phase” and the output voltage “Vo” is detected. In operation, Driver Logic 13 develops the gating signals for M1, and M2, in response to the transitions in the PWM input signal. By alternating the current from inductor L into the output circuit capacitor Co, and into ground, the output voltage may be regulated by switching signals. The boost converter can provide an output voltage Vo higher than the supply voltage PVCC.
FIG. 6 depicts a timing diagram illustrating the operation of the boost topology converter of FIG. 5. In FIG. 6, the top trace labeled “phase (V)” depicts a detailed timing view of the voltage at the node phase in FIG. 5. The next trace down, labeled “phase, Vout (V)”, depicts a timing diagram of the voltages at those nodes taken together. The trace labeled IL (A) is a timing diagram of the current IL for a simulated boost circuit in configured in a typical configuration. The bottom trace illustrates the gating signal voltages GSR, GLS.
As can be seen in FIG. 6, when the phase voltage and the output voltage are equal and the gate signal GSR is high, at time T1, the current IL is nearing the zero crossing point. In this simulation the GSR signal to the SR device is gated OFF by the operation of the comparator 17 and the current IL is not permitted to become negative, thereby preventing the loss that would otherwise occur (capacitor Co would discharge into the converter circuit.)
FIGS. 7 and 8 depict how voltage sensing of the phase node to detect the zero crossing point of the current IL can be applied to an inverting, and a non inverting buck-boost converter, respectively. FIG. 7 depicts the conventional inverting buck boost topology. Again identical reference designators are used for the like elements from FIGS. 3 and 5. The buck-boost circuit may be used to regulate the output voltage to be more, or less than, the input voltage (inverted) and so has utility in certain applications beyond the simple buck, or boost, converter topologies.
FIG. 8 is a prior art non-inverting buck-boost converter circuit. As is known to those skilled in the art, by providing two distinct stages, the buck boost converter may be configured in a non-inverting mode. A separate buck and boost synchronous rectifier SRBU and SRBO is provided, and phase node sensing is performed for each of these using the comparators 18, and 17; but the zero crossing detection approaches are generally the same as those described above.
FIG. 9 illustrates the timing diagram for a simulation using the inverting buck-boost converter topology of FIG. 7; again illustrating the phase voltage sensing for the zero crossing detection, and the comparator providing diode emulation. As can be seen at the time T1, the comparator and AND gate are turning the gate signal to the SR device OFF to prevent the current IL from flowing back into the converter circuit.
Thus the same principle for detecting the zero crossing point is applied to the buck, boost and buck-boost switching converter topologies in the prior art approaches. Voltage sensing on the phase node is performed and compared to another available circuit voltage selected in order to determine the zero crossing point for the output current IL. Generally, the SR gating signal is then affected by turning off the conduction path to prevent negative current flow, thus the SR device emulates the diode of the asynchronous converter. The negative current flow that would otherwise discharge the output capacitor Co unnecessarily is prevented.
The voltage sensing circuits for zero crossing detection in the switched converters of the prior art are known to be subject to inefficient operations due to delays in logic circuitry, variations in power, temperature and process, and variations in device parameters which continue to cause less than desirable operation.
A continuing need thus exists for an efficient and reliable circuit and methods to control the operations of a switching converter circuit in DCM mode.